module sel_driver(
    input               clk         ,
    input               rst_n       ,
    input      [23:0]   dis_data    ,   //寄存器模块所创值
    output reg [5:0]    sel         ,   //片选
    output reg [7:0]    dig             //段选
);

    parameter zero = 7'b100_0000,
              one  = 7'b111_1001,
              two  = 7'b010_0100,
              three= 7'b011_0000,
              four = 7'b001_1001,
              five = 7'b001_0010,
              six  = 7'b000_0010,
              seven= 7'b111_1000,
              eight= 7'b000_0000,
              nine = 7'b001_0000,
              A    = 7'b000_1000,   //A
              B    = 7'b000_0011,   //b
              C    = 7'b100_0110,   //C
              D    = 7'b010_0001,   //d
              E    = 7'b000_0110,   //E
              F    = 7'b000_1110;   //F

    parameter TIME_20us=1000;       //数码管切换

    reg  [9:0]  cnt;
    wire        add_cnt;
    wire        end_cnt;

    reg         dot;                //小数点
    reg   [3:0]      data;               //寄存数据             

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            cnt=0;
        end
        else if(add_cnt)begin
            if(end_cnt)begin
                cnt<=0;
            end
            else begin
                cnt<=cnt+1;
            end
        end
        else begin
            cnt<=cnt;
        end
    end
    assign add_cnt=1'b1;
    assign end_cnt=add_cnt&&cnt==TIME_20us-1;

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            sel<=6'b011_111;
        end
        else if(end_cnt)begin
            sel<={sel[0],sel[5:1]};
        end
        else begin
            sel<=sel;
        end
    end
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            dot<=1'b1;
            data<=4'hf;
        end
        else begin
            case(sel)
                6'b011_111:begin data<=dis_data[3:0]    ;   dot<=1'b1;end
                6'b101_111:begin data<=dis_data[7:4]    ;   dot<=1'b1;end
                6'b110_111:begin data<=dis_data[11:8]   ;   dot<=1'b0;end
                6'b111_011:begin data<=dis_data[15:12]  ;   dot<=1'b1;end
                6'b111_101:begin data<=dis_data[19:16]  ;   dot<=1'b0;end
                6'b111_110:begin data<=dis_data[23:20]  ;   dot<=1'b1;end
                default   :begin data<=4'hf             ;   dot<=1'b1;end
            endcase
        end
    end

    always @(*)begin
        if(!rst_n)begin
            dig<=8'hff;
        end
        else begin

            case(data)
                4'd0       :   dig<={dot,zero };
                4'd1       :   dig<={dot,one  };
                4'd2       :   dig<={dot,two  };
                4'd3       :   dig<={dot,three};
                4'd4       :   dig<={dot,four };
                4'd5       :   dig<={dot,five };
                4'd6       :   dig<={dot,six  };
                4'd7       :   dig<={dot,seven};
                4'd8       :   dig<={dot,eight};
                4'd9       :   dig<={dot,nine };
                4'd10      :   dig<={dot,A    };
                4'd11      :   dig<={dot,B    };
                4'd12      :   dig<={dot,C    };   
                4'd13      :   dig<={dot,D    };   
                4'd14      :   dig<={dot,E    };   
                4'd15      :   dig<={dot,F    };   
                default :   dig<=8'hff;
            endcase
        end        
    end
endmodule